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Subject: sidsc-design specialization (reusing components)
- From: "Park Seth-R01164" <seth.park@freescale.com>
- To: "Semiconductor Information Design Subcommittee" <dita-sidsc@lists.oasis-open.org>
- Date: Tue, 2 Jun 2009 08:52:57 -0700
New structure:
sidsc-design
This is a proposed
structure for the initial public release of the SIDSC
plugin.
Problem
statement
The SIDSC data model
does not provide good support for reusing components. There are several
usecases that the proposed sidsc-design map addresses:
1. Supply a base
address for each component on a design. Currently, it is hard-coded and can be
filtered via select-atts.
2. Provide a
collection of components.
3. Define RTL
parameters.
Inspiration:
IP-XACT
IP-XACT has a
<design> element that satisfies the usecases above. Here is how the
specification describes the design element:
"An IP-XACT design
is the central placeholder for the assembly of component objects meta-data. A
design describes a list of components referenced by this description, their
configuration, and their interconnections to each other. The interconnections
may be between interfaces or between ports on a component. A
design description is analogous to a schematic of
components."
This is exactly what
we need.
Desired
response
Please have a look
at this proposal and be ready for discussion at the next sidsc call. I know I'm
throwing a bunch of last minute items at you, but these are real issues that
I've encountered using the schema in a production environment. I think it will
benefit all members/users... and, the work is already done and
documented.
Sample
RTL (from
wikipedia.com)
module Div20x (rst,
clk, cet, cep, count,tc);
// TITLE 'Divide-by-20 Counter with enables'
//
enable CEP is a clock enable only
// enable CET is a clock enable and
//
enables the TC output
// a counter using the Verilog
language
parameter size = 5;
parameter length =
20;
input rst; // These
inputs/outputs represent
Sample
IP-XACT design element
<design>
<vendor>spiritconsortium.org</vendor>
<library>Leon2RTL</library>
<name>design_Leon2Platform</name>
<version>3.0</version>
<componentInstances>
<componentInstance>
<instanceName>uahbbus</instanceName>
<componentRef vendor="spiritconsortium.org" library="Leon2RTL"
name="ahbbus22" version="1.3"/>
<configurableElementValues>
<configurableElementValue
referenceId="defmast">0</configurableElementValue>
<configurableElementValue
referenceId="range_slv0_mirror">0x00040000</configurableElementValue>
<configurableElementValue
referenceId="range_slv1_mirror">0x00009000</configurableElementValue>
</configurableElementValues>
</componentInstance>
</componentInstances>
Sample SIDSC
design
<sidsc-design>
<component-ref
base-address="0"
href="TPM.xml">
<parameter>
<key>size</key>
<value>5</value>
</parameter>
<parameter>
<key>length</key>
<value>20</value>
</parameter>
</component-ref>
<component-ref base-address="1"
href="SCI.xml">
</component-ref>
</sidsc-design>
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