RE: [PATCH v2 0/2] transport-pci: Introduce legacy registers access using AQ

[Parav Pandit <parav@nvidia.com>]

> From: Michael S. Tsirkin <mst@redhat.com>
> Sent: Thursday, May 11, 2023 8:55 AM

> > 1) device features
> > 2) driver features
> > 3) queue address
> > 4) queue size
> > 5) queue select
> > 6) queue notify
> > 7) device status
> > 8) ISR status
> > 9) config msix
> > 10) queue msix
> > 11) device configuration space
> >
#9 may not even go to the group owner device.
What do we gain from bisecting it?
Every new additional needs involvement of the hypervisor as Michael noted below on "effort" point.

The register offset and read/write is far simpler interface for hypervisor.

Not to do cross register access is what we need to define in the spec for 1.x or future things.

> > It focuses on the facilities instead of transport specific details
> > like registers (we don't even need legacy registers in this case), I
> > gives more deterministic behavior so we don't need to care about the
> > cross registers read/write.
> 
> This needs thought, it is definitely more work.  Effort that could be maybe spent
> on new features.  What is the motivation here? supporting legacy mmio guests?