RE: [virtio-dev] Re: [PATCH v3 0/3] transport-pci: Introduce legacy registers access using AQ

[Parav Pandit <parav@nvidia.com>]

> From: Michael S. Tsirkin <mst@redhat.com>
> Sent: Tuesday, June 6, 2023 7:56 AM
> 
> On Mon, Jun 05, 2023 at 10:12:59PM +0000, Parav Pandit wrote:
> > Rolling v4 now.
> 
> Great thanks! I think the result will be in a good shape from the ABI point of
> view. Good job!
> 
Thanks.

> I think so far Jason was the only one with significant comments on the series so
> let's see what he says.
> 
> From my personal POV what will be left to do to get this feature ready for
> merging would be
> 
> - tightening the language:
> - thinking of and addressing all kind of corner cases.
>
> 
> Since by now from our email discussions I have I think a decent understanding
> of how the feature is supposed to work I understand how these things work but I
> think there are still things that would be a bit unclear for an unprepared reader.
> 
Many aspects are covered in the cover letter.

> Just to give a random example, there's no explicit time where the member kind
> of switches to the legacy/back to modern mode. I am guessing setting DRIVER
> bit through legacy interface does this. We'll want to list that.
> 
Switch between the two is the same as today how a transitional device accesses both the register space.
Hypervisor level vfio tiny stub driver is not involved in such switchover as today.

> I'll try to help find these issues and maybe even suggest wording.
> 
Sure. That will be great.

> I've delayed commenting on these until the high level design is agreed on,
> didn't want to make you waste time on polishing as the patches undergo
> significant changes, and I suggest you do the same in v4: let's make sure there's
> a wide agreement on the ABI then focus on the spec language.

I agree, now that we agree on the design and ABI, lets polish above aspects you told in v4.
I posted v4.