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Subject: Re: [PATCH v9 4/4] transport-pci: Introduce group legacy group member config region access
On Wed, Jul 05 2023, Parav Pandit <parav@nvidia.com> wrote: > diff --git a/admin-cmds-legacy-interface.tex b/admin-cmds-legacy-interface.tex > index 09001d5..571b256 100644 > --- a/admin-cmds-legacy-interface.tex > +++ b/admin-cmds-legacy-interface.tex > @@ -150,7 +150,7 @@ \subsubsection{Legacy Interfaces}\label{sec:Basic Facilities of a Virtio Device > by the device. > > Refer to the specific transport section for the definition of the > -\field{region_data}. > +\field{region_data}. For PCI transport refer to section \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / Legacy Interface: Group Member Device Configuration Region Access}. "For the PCI transport, refer to..." > > This command is currently only defined for the PCI SR-IOV group type. > (...) > diff --git a/transport-pci-legacy-regs.tex b/transport-pci-legacy-regs.tex > new file mode 100644 > index 0000000..e4f70c9 > --- /dev/null > +++ b/transport-pci-legacy-regs.tex > @@ -0,0 +1,41 @@ > +\subsection{Legacy Interface: Group member device Configuration Region Access}\label{sec:Virtio Transport Options / Virtio Over PCI Bus / Legacy Interface: Group Member Device Configuration Region Access} > + > +The PCI owner device or the member device or both supports driver notifications using s/supports/support/ > +a notification region defined in the \field{struct virtio_pci_notify_region}. s/in the/in/ > + > +In \field{struct virtio_virtio_admin_cmd_legacy_notify_query_entry}, > +\field{region_data} is defined as following: > + > +\begin{lstlisting} > +struct virtio_pci_legacy_notify_region { > + u8 owner; /* When set to 1, notification region is of the owner device */ > + u8 bar; /* BAR of the member or owner device */ > + u8 padding[6]; > + le64 offset; /* Offset within bar. */ > +}; > +\end{lstlisting} > + > +The group owner device hardwire VF BAR0 in the SR-IOV Extended capability. s/hardwire/hardwires/ > + > +The group member device does not use PCI BAR0 in various Virtio PCI capabilities "in the various" caps? Or "in some of the" caps? > +listed in section \ref{sec:Virtio Transport Options / Virtio Over PCI Bus / Virtio Structure PCI Capabilities}.
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