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Subject: Re: [virtio-dev][PATCH V9 2/2] virtio-spi: add the device specification
On Tue, Dec 12 2023, Haixu Cui <quic_haixcui@quicinc.com> wrote: [BTW: A changelog would be useful, either in the patch or in the cover letter.] > The Virtio SPI (Serial Peripheral Interface) device is a virtual > SPI controller that allows the driver to operate and use the SPI > controller under the control of the host. > > This patch adds the specification for virtio-spi. > > Signed-off-by: Haixu Cui <quic_haixcui@quicinc.com> > Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> > --- > device-types/spi/description.tex | 281 ++++++++++++++++++++++++ > device-types/spi/device-conformance.tex | 7 + > device-types/spi/driver-conformance.tex | 7 + > 3 files changed, 295 insertions(+) > create mode 100644 device-types/spi/description.tex > create mode 100644 device-types/spi/device-conformance.tex > create mode 100644 device-types/spi/driver-conformance.tex > > diff --git a/device-types/spi/description.tex b/device-types/spi/description.tex Please move inclusion of this new file into content.tex here, instead of including a not-yet-existing file in the previous patch. (...) > +\field{mode_func_supported} indicates whether the following features are supported or not: > + bit 0-1: CPHA feature, > + 0b00: invalid, must support as least one CPHA setting. > + 0b01: supports CPHA=0 only; > + 0b10: supports CPHA=1 only; > + 0b11: supports CPHA=0 and CPHA=1; > + > + bit 2-3: CPOL feature, > + 0b00: invalid, must support as least one CPOL setting. > + 0b01: supports CPOL=0 only; > + 0b10: supports CPOL=1 only; > + 0b11: supports CPOL=0 and CPOL=1; > + > + bit 4: chipselect active high feature, 0 for unsupported and 1 for supported, > + chipselect active low must always be supported. > + > + bit 5: LSB first feature, 0 for unsupported and 1 for supported, MSB first must always be > + supported. > + > + bit 6: loopback mode feature, 0 for unsupported and 1 for supported, normal mode > + must always be supported. > + > +Note: CPOL is clock polarity and CPHA is clock phase. If CPOL is 0, the clock idles at the logical > +low voltage, otherwise it idles at the logical high voltage. CPHA determines how data is outputted > +and sampled. Shouldn't you also specify what CPHA==0 and CPHA==1 mean? (...) > +VIRTIO_SPI_TRANS_ERR indicates a transfer error, which means that the parameters are all > +valid but the trasnfer process failed. s/trasnfer/transfer/ LGTM otherwise. Does anybody else have comments?
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