Re: [virtio-comment] Hardware friendly proposals from Intel for packed-ring-layout

["Michael S. Tsirkin" <mst@redhat.com>]

On Thu, Aug 24, 2017 at 07:53:15PM +0800, Tiwei Bie wrote:
> Rx Fixed Buffer Sizes
> =====================
> 
> ## Current proposal
> 
> * Driver is free to choose whatever buffer sizes it wishes for Tx and
>   Rx buffers
> * Theoretically within a ring, a driver could have different buffer sizes
> 
> ## New proposal
> 
> * Driver negotiates with device the size of a Rx buffer for a ring
>     - Each descriptor in that ring will have same size buffer
>     - Different rings can have different sized buffers

What's the motivation for this?  In our testing dynamically
sized entries perform better in contrained environments
such as the linux kernel where packets are queued at
a huge number of independent application sockets.

It seems that device can easily cache the last size to speed up
operation.


> Data Alignment Boundaries
> =========================
> 
> ## Current proposal
> 
> * Driver is free to choose data buffer alignment to any byte boundary
> 
> ## New proposal
> 
> * Stipulate a fixed alignment for the data buffer

Again motivation seems to be missing. Saving PCI bandwidth
isn't going to help if it means driver will then incur more
cache misses on access.


-- 
MST