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Subject: RE: [PATCH 00/11] Introduce transitional mmr pci device
> From: Michael S. Tsirkin <mst@redhat.com> > Sent: Monday, April 3, 2023 10:53 AM > > On Fri, Mar 31, 2023 at 05:43:11PM -0400, Parav Pandit wrote: > > > I can not say I thought about this > > > deeply so maybe there's some problem, or maybe it's a worse approach > > > - could you comment on this? It looks like this could be a smaller > > > change, but maybe it isn't? Did you consider this option? > > > > We can possibly let both the options open for device vendors to implement. > > > > Change wise transport VQ is fairly big addition for both hypervisor > > driver and also for the device. > > OTOH it is presumably required for scalability anyway, no? No. Most new generation SIOV and SR-IOV devices operate without any para-virtualization. > And presumably it can all be done in firmware ... > Is there actual hardware that can't implement transport vq but is going to > implement the mmr spec? > Nvidia and Marvell DPUs implement MMR spec. Transport VQ has very high latency and DMA overheads for 2 to 4 bytes read/write. And before discussing "why not that approach", lets finish reviewing "this approach" first.
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