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Subject: Fwd: Virtio-1.1 Ring Layout
Hi, Attached is an evolving proposal dealing with FPGA/HW-friendly implementation, from Kully Dhanoa, Intel. Thanks, Amnon
Attachment:
virtio_1_1_hw_v2_0.pptx
Description: virtio_1_1_hw_v2_0.pptx
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