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Subject: [PATCH] Define all MMIO registers as little endian

Port of draft commit 88f37f9ec178b664213b77211fec03687b87958b.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
 virtio-v1.0-wd01-part1-specification.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/virtio-v1.0-wd01-part1-specification.txt b/virtio-v1.0-wd01-part1-specification.txt
index a3ee054..3d69fd4 100644
--- a/virtio-v1.0-wd01-part1-specification.txt
+++ b/virtio-v1.0-wd01-part1-specification.txt
@@ -993,8 +993,9 @@ Virtual queue size is the number of elements in the queue,
 therefore size of the descriptor table and both available and 
 used rings.
-The endianness of the registers follows the native endianness of 
-the Guest. Writing to registers described as "R" and reading from 
+All register values are organized as Little Endian.
+Writing to registers described as "R" and reading from
 registers described as "W" is not permitted and can cause 
 undefined behavior.

> Define virtio-mmio registers as LE
> ----------------------------------
>                 Key: VIRTIO-6
>                 URL: http://tools.oasis-open.org/issues/browse/VIRTIO-6
>             Project: OASIS Virtual I/O Device (VIRTIO) TC
>          Issue Type: Improvement
>            Reporter: Rusty Russell
>            Assignee: Pawel Moll
> As per 88f37f9ec178b664213b77211fec03687b87958b.

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