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Subject: [OASIS Issue Tracker] (VIRTIO-104) PCI Operation
[ https://tools.oasis-open.org/issues/browse/VIRTIO-104?page=com.atlassian.jira.plugin.system.issuetabpanels:all-tabpanel ]
Michael Tsirkin updated VIRTIO-104:
-----------------------------------
Assignee: (was: Michael Tsirkin)
Environment: Andrew Thornton <andrewth@google.com> (was: Andrew Thornton <andrewth@google.com>)
Description:
4.1.3.1 Device Initialization
The driver must enable PCI bus mastering before programming any virtio queues. (Otherwise the device shouldn’t be accessing memory but this has been historically ignored). What happens when the bus master enable bit is cleared when virtio is running?
4.1.3.1.1 Virtio Device Configuration Layout Detection
Instead of using PCI_CAP_ID_VNDR could a unique capability be allocated from the PCI SIG? It would be useful to be able to identify the VIRTIO capability without special driver knowledge.
4.1.3.1.3 Virtio Configuration
What happens when an invalid size is written to the queue_size register?
4.1.3.4 Notification of Device Configuration Changes
What portion of configuration space should be re-examined? We assume just the device specific fields and not BARs or other generic configuration. The spec should clarify this.
In the MSI-X enablement case no mention of setting an interrupt status bit. In the case where a unique MSI isn’t allocated to this table entry how does the driver detect this?
Clarification of runtime device error handling
When an error occurs such as invalid descriptor or a DMA to an invalid address what does the device do? i.e. does it continue processing the current descriptor or does it halt (our preference). How does the driver recover the device? Is a virtio reset sufficient? What about inflight DMAs?
was:
4.1.3.1 Device Initialization
The driver must enable PCI bus mastering before programming any virtio queues. (Otherwise the device shouldn’t be accessing memory but this has been historically ignored). What happens when the bus master enable bit is cleared when virtio is running?
4.1.3.1.1 Virtio Device Configuration Layout Detection
Instead of using PCI_CAP_ID_VNDR could a unique capability be allocated from the PCI SIG? It would be useful to be able to identify the VIRTIO capability without special driver knowledge.
4.1.3.1.3 Virtio Configuration
What happens when an invalid size is written to the queue_size register?
4.1.3.4 Notification of Device Configuration Changes
What portion of configuration space should be re-examined? We assume just the device specific fields and not BARs or other generic configuration. The spec should clarify this.
In the MSI-X enablement case no mention of setting an interrupt status bit. In the case where a unique MSI isn’t allocated to this table entry how does the driver detect this?
Clarification of runtime device error handling
When an error occurs such as invalid descriptor or a DMA to an invalid address what does the device do? i.e. does it continue processing the current descriptor or does it halt (our preference). How does the driver recover the device? Is a virtio reset sufficient? What about inflight DMAs?
Proposal: 1401572627-19287-1-git-send-email-mst@redhat.com">http://mid.gmane.org/1401572627-19287-1-git-send-email-mst@redhat.com
> PCI Operation
> -------------
>
> Key: VIRTIO-104
> URL: https://tools.oasis-open.org/issues/browse/VIRTIO-104
> Project: OASIS Virtual I/O Device (VIRTIO) TC
> Issue Type: Sub-task
> Affects Versions: virtio 1.0 csprd01
> Environment: Andrew Thornton <andrewth@google.com>
> Reporter: Rusty Russell
>
> 4.1.3.1 Device Initialization
> The driver must enable PCI bus mastering before programming any virtio queues. (Otherwise the device shouldn’t be accessing memory but this has been historically ignored). What happens when the bus master enable bit is cleared when virtio is running?
> 4.1.3.1.1 Virtio Device Configuration Layout Detection
> Instead of using PCI_CAP_ID_VNDR could a unique capability be allocated from the PCI SIG? It would be useful to be able to identify the VIRTIO capability without special driver knowledge.
> 4.1.3.1.3 Virtio Configuration
> What happens when an invalid size is written to the queue_size register?
> 4.1.3.4 Notification of Device Configuration Changes
> What portion of configuration space should be re-examined? We assume just the device specific fields and not BARs or other generic configuration. The spec should clarify this.
> In the MSI-X enablement case no mention of setting an interrupt status bit. In the case where a unique MSI isn’t allocated to this table entry how does the driver detect this?
> Clarification of runtime device error handling
> When an error occurs such as invalid descriptor or a DMA to an invalid address what does the device do? i.e. does it continue processing the current descriptor or does it halt (our preference). How does the driver recover the device? Is a virtio reset sufficient? What about inflight DMAs?
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