[Date Prev] | [Thread Prev] | [Thread Next] | [Date Next] -- [Date Index] | [Thread Index] | [List Home]
Subject: [PATCH v3 6/9] virtio-iommu: Add RISC-V page tables
The RISC-V IOMMU allows a guest to attach either a single page directory or, when PASID is supported, a process directory (PASID table). Add the PROBE and ATTACH_TABLE descriptions to support RISC-V. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> --- v2->v3: Drop capabilities defines, best left to virtio_iommu.h --- device-types/iommu/description.tex | 3 + device-types/iommu/pgtable-riscv.tex | 92 ++++++++++++++++++++++++++++ introduction.tex | 3 + 3 files changed, 98 insertions(+) create mode 100644 device-types/iommu/pgtable-riscv.tex diff --git a/device-types/iommu/description.tex b/device-types/iommu/description.tex index 0ec067c..6fcd296 100644 --- a/device-types/iommu/description.tex +++ b/device-types/iommu/description.tex @@ -408,6 +408,7 @@ \subsubsection{ATTACH_TABLE request}\label{ref:Device Types / IOMMU Device / Dev #define VIRTIO_IOMMU_ATTACH_TABLE_ARM_SMMU3 1 #define VIRTIO_IOMMU_ATTACH_TABLE_INTEL_PT 2 +#define VIRTIO_IOMMU_ATTACH_TABLE_RISCV 4 \end{lstlisting} Attach an endpoint to a domain, in the same way as an ATTACH @@ -999,6 +1000,7 @@ \subsubsection{PROBE properties}\label{sec:Device Types / IOMMU Device / Device #define VIRTIO_IOMMU_PROBE_T_RESV_MEM 1 #define VIRTIO_IOMMU_PROBE_T_HW_ARM_SMMU3 2 #define VIRTIO_IOMMU_PROBE_T_HW_INTEL_VTD 3 +#define VIRTIO_IOMMU_PROBE_T_HW_RISCV 4 \end{lstlisting} \paragraph{Property RESV_MEM}\label{sec:Device Types / IOMMU Device / Device operations / PROBE properties / RESVMEM} @@ -1151,3 +1153,4 @@ \subsection{Acceleration}\label{sec:Device Types / IOMMU Device / Acceleration} \input{device-types/iommu/pgtable-arm} \input{device-types/iommu/pgtable-intel} +\input{device-types/iommu/pgtable-riscv} diff --git a/device-types/iommu/pgtable-riscv.tex b/device-types/iommu/pgtable-riscv.tex new file mode 100644 index 0000000..4118bf6 --- /dev/null +++ b/device-types/iommu/pgtable-riscv.tex @@ -0,0 +1,92 @@ +\subsubsection{RISC-V IOMMU tables}\label{sec:Device Types / IOMMU Device / Acceleration / RISC-V} + +Attach Process Directory Table (PDT) and first-stage page tables in the format +described in the \hyperref[intro:RISCV-IOMMU]{RISC-V IOMMU Architecture +Specification v1.0}. + +\paragraph{PROBE properties for RISC-V IOMMU}\label{sec:Device Types / IOMMU Device / Acceleration / RISC-V / PROBE} + +The PROBE property VIRTIO_IOMMU_PROBE_T_HW_RISCV provides +information about a RISC-V IOMMU. + +\begin{lstlisting} +struct virtio_iommu_probe_hw_riscv { + struct virtio_iommu_probe_property head; + u8 gxl; + u8 reserved[3]; + le64 capabilities; +}; + +\end{lstlisting} + +The \field{capabilities} field correspond to the RISC-V IOMMU capabilities +register. + +Field \field{gxl} corresponds to the IOMMU fctl.GXL +configuration, and describes the virtual-memory schemes +available. If \field{gxl} is 1, the driver sets SXL to 1 when +configuring page tables. + +\paragraph{ATTACH_TABLE request for RISC-V IOMMU}\label{sec:Device Types / IOMMU Device / Acceleration / RISC-V / ATTACH_TABLE} + +\begin{lstlisting} +struct virtio_iommu_req_attach_table_riscv { + struct virtio_iommu_req_head head; + le32 domain; + le32 endpoint; + u8 format; + u8 reserved[3]; + le64 tc; + le64 ta; + le64 fsc; + u8 reserved[84]; + struct virtio_iommu_req_tail tail; +}; + +#define VIRTIO_IOMMU_HW_RISCV_TC_PDTV (1 << 5) +#define VIRTIO_IOMMU_HW_RISCV_TC_SADE (1 << 8) +#define VIRTIO_IOMMU_HW_RISCV_TC_DPE (1 << 9) +#define VIRTIO_IOMMU_HW_RISCV_TC_SBE (1 << 10) +#define VIRTIO_IOMMU_HW_RISCV_TC_SXL (1 << 11) + +#define VIRTIO_IOMMU_HW_RISCV_TA_PSCID_SHIFT 12 +#define VIRTIO_IOMMU_HW_RISCV_TA_PSCID_MASK 0xfffff + +#define VIRTIO_IOMMU_HW_RISCV_FSC_MODE_SHIFT 60 +#define VIRTIO_IOMMU_HW_RISCV_FSC_MODE_MASK 0xf +#define VIRTIO_IOMMU_HW_RISCV_FSC_PPN_MASK 0xfffffffffff + +/* When VIRTIO_IOMMU_HW_RISCV_TC_PDTV == 0 */ +#define VIRTIO_IOMMU_HW_RISCV_FSC_MODE_SV39 8 +#define VIRTIO_IOMMU_HW_RISCV_FSC_MODE_SV48 9 +#define VIRTIO_IOMMU_HW_RISCV_FSC_MODE_SV57 10 +#define VIRTIO_IOMMU_HW_RISCV_FSC_MODE_SV32 8 + +/* When VIRTIO_IOMMU_HW_RISCV_TC_PDTV == 1 */ +#define VIRTIO_IOMMU_HW_RISCV_FSC_MODE_PD8 1 +#define VIRTIO_IOMMU_HW_RISCV_FSC_MODE_PD17 2 +#define VIRTIO_IOMMU_HW_RISCV_FSC_MODE_PD20 3 +\end{lstlisting} + +Field \field{format} is VIRTIO_IOMMU_ATTACH_TABLE_RISCV. + +The RISC-V IOMMU supports two modes: + +\begin{description} + \item[VIRTIO_IOMMU_HW_RISCV_TC_PDTV = 0] + Field \field{fsc} contains a page directory and the paging + mode. Field \field{ta} contains a PSCID. + + \item[VIRTIO_IOMMU_HW_RISCV_TC_PDTV = 1] + Field \field{fsc} contains the process directory and the + process table layout. Field \field{ta} is zero. +\end{description} + +\paragraph{INVALIDATE request for RISC-V IOMMU}\label{sec:Device Types / IOMMU Device / Acceleration / RISC-V / INVALIDATE} + +When a process directory is attached, bits [19:0] of \field{id} +in an INVALIDATE request correspond to the PSCID of the page +directory. + +\todo{What are valid invalidate scope and caches values, +depending on pdtv? Leaf flag unsupported?} diff --git a/introduction.tex b/introduction.tex index 9d0f5c5..1957611 100644 --- a/introduction.tex +++ b/introduction.tex @@ -107,6 +107,9 @@ \section{Normative References}\label{sec:Normative References} \phantomsection\label{intro:VT-Directed-IO}\textbf{[VT-Directed-IO]} & Intel Virtualization Technology for Directed I/O \newline\url{https://cdrdv2.intel.com/v1/dl/getContent/671081} \\ + \phantomsection\label{intro:RISCV-IOMMU}\textbf{[RISCV-IOMMU]} & + RISC-V IOMMU Specification + \newline\url{https://github.com/riscv-non-isa/riscv-iommu/releases} \\ \phantomsection\label{intro:rfc2784}\textbf{[RFC2784]} & Generic Routing Encapsulation. This protocol is only specified for IPv4 and used as either the payload or delivery protocol. -- 2.43.0
[Date Prev] | [Thread Prev] | [Thread Next] | [Date Next] -- [Date Index] | [Thread Index] | [List Home]